Pacman Sync Bus Schematics

[deadmatty]

I'm trying transcribe the Pacman Sync Bus and V-RAM Addresser schematics in to KiCad with a view to getting some PCBs printed (and learning KiCad)... However, I've started to see discrepancies between Pin numbers and pin descriptions. Is anyone familiar with this Schematic able to confirm which is correct, number or description? I'm using the one from the Ms Pacman Manual as it's a better scan, but I think the Pacman Manual is the same...

 

[qjuk]

Pin 9 (normally the Y3 data output) on the LS139 is not connected on my Sync Buss Board. Pin 12 of the LS139 does go to pin 2 on the LS74.

On the LS74, the CLR pin 1 is also not connected, so that appears to be an error on the schematic.

 

[deadmatty]

Thanks for that The CLR Pin is routing to a pull-up resistor on the schem. It's the same on the CLR pins on both 74s

 

[qjuk]

Just had another closer look at my board now, there’s actually a very fine track underneath the 74 chip to pin 1, so it is connected. It’s near impossible to see and I can’t say for sure exactly where the track goes without desoldering the chip. Multi-meter is beeping continuity between pins 1, 4, 10 and 13 on the same chip.

It’s exactly the same on the other 74, Pin 1 is showing continuity between 1,4, 10 and 13 also.