Without the novelty of trying to fix this board I would probably be out on the streets robbing old grannies or smashing up bus shelters or something so probably just best to stick with it for a while longer...
Looking at the 2nd 74LS161... H16...
So this is fed from pin 15 of H15 which is Ripple Carry Out... i.e. Carry... H15 is counting... E, F, 0, E, F, 0, ... with carry on the 0...
Here's H16...

It's all over the place! Something not good here. (NOTE: I have removed all the lurking small caps at this stage).
I really need pin 13 to be the pixel clock 6MHz divided by 4 to give the 6809 E clock... but here it's a mess and looking more like 3MHz...
Now I'm going to go very off piste here and say I think the design is wrong!
Firstly H16 is driven from the NOT of the H15 clock (from pin 12 of the 74LS04), so it is 180 degrees out of phase with H15.. But look at the signals that drive it...
74LS161 is positive edge triggered... so there is a count when CH6 (aka pin 7 (and pin 10)) are HI but at the trailing edge of CH6 (which is the Pixel Clock) there is a point at which the edges are VERY close together. I think that's a problem! Now people cleverer than me seem to know how to fix that with small caps but I don't so I think I'm going to do something very drastic... I'm going to cut the trace and drive H16 with the SAME clock as H15.
My reasoning is that the RCO (aka TC aka pin 15) output has long enough propagation, according to datasheet 23ns typical, that we end up dangerously close to the rising edge of the NOTed clock; by using the other phase we are going to be safer (although one half clock delayed)...
I wonder how this is going to work out... let me know if you think I've lost the plot!