Well if people are interested... a quick diversion into Konami 081 Theory of Operation...
Juno First and Tutankham have a 4116 DRAM based Video Frame Buffer and being DRAM it needs refresh and being 4116's it needs row and column addresses each 7 bits wide. On the legit items this co-ordination is provided by a Konami 081 custom but on the bootlegs it is done in 74 series logic. Interesting the implementations do seem to differ between the bootlegs... but more of that later.
The Konami 081 (or equivalent) basically divides time into 4 sections repeatedly. The first is CPU access... here MXB is low allowing the CPU to drive the address bus. MXA is flipped half way through to split the 14 bits into two pairs of 7 bits and these are loaded on the falling edges of RAS and CAS. During the second half the Video counters drive the address bus and the same effect is achieved. So the video reads and the CPU read/writes are interleaved. The whole video read cycle goes around fast enough that the DRAM stays refreshed (all it needs is a read).
The timing of the edges of MXA, MXB, RAS and CAS relative to each other are critical and that's what I am working on currently...
What is interesting is that if this were pure logic in the implementation then the edges would not line up correctly and this is what I am investigating currently... I think this is the purpose of the 300pF capacitor and I suspect my problem is the specific 74LS161 I have swapped... the 300pF acts as an edge delay but is dependent on the input impedance of the counter (to form an RC circuit)... but I am reverse engineering as I go so it's a slow process.
And I have to find the 300pF I removed a year ago... must have put it somewhere!
