Juno First Boot Leg

cliff_poole

cliff_poole

Active member
vacBacker
Feedback
6 (100%)
Credits
1,069CR
Yes !. I can confirm that mine does have those capacitors.

I dug my board out when you started this thread and gave it another good going over before giving up again (mine fails to run code). Your information about the 081 custom and where it sits was very useful.

In my case, I wasn't liking the look of the waveforms on the chips with the added capacitors. I temporarily removed them so that I could test the chips with my ABI. The chips passed in circuit testing and the waveforms looked much better on the scope without the caps. Before abandoning it again, I put the caps back so I didn't forget where they went.
 
cliff_poole

cliff_poole

Active member
vacBacker
Feedback
6 (100%)
Credits
1,069CR
My problem at the moment is that, years back when I first started troubleshooting, I programmed a new set of the three GALs. I have a vague memory of encountering problems while programming. Stupidly, I didn't make any notes of where the original chips went, so although I still have them, don't know which order they go back. My originals are numbered 1 to 3, but I see yours are not.
 
N

NivagSwerdna

Active member
Feedback
1 (100%)
Credits
712CR
PALs are (when looking at the board with the ROMs along the top and the XTAL bottom right)

Top left 5C
Bottom left 5F
Right 9F

Juno First (bootleg) -

wiki.pldarchive.co.uk wiki.pldarchive.co.uk

The equations are quite interesting, 5F is used here with mangled outputs on p12, p14, p19 and p18 which are actually tri-state outputs controlled by p3... These same set of equations have been used elsewhere but with outputs on p13, p15, p16 and p19 which are the same but not tri-stated.

Anyway 5F and 9F do the instruction mangling when LIC is high, 5C is address decide.

I think I'm starting to understand the caps and also I think I need to switch back to LS series for the 161s here to get back to original input impedance. I have ordered some small caps and will try and add some delay to RAS and work from there.. I'm feeling 30pF for my first attempt.
 
N

NivagSwerdna

Active member
Feedback
1 (100%)
Credits
712CR
r-type said:
I wish I knew what you were going on about with any of this. I'm impressed anyway. Keep it up.
Click to expand...
I will try and explain as I work through it... Essentially the addressing of the dynamic RAM is multiplexed into two pairs of 7 bit addresses rather than having 14 pins but for the address to get locked in there are two signals RAS and CAS. When RAS goes low it locks in the first seven bits and when CAS goes low it locks in the second seven bits.
Now the Konami 081 generates these signals but here it is implemented in logic. The first point is that the multiplexing of the low and high seven bit addresses is controlled by MXA and then RAS should happen when the address has stabilized. Here the RAS is generated by NOT MXA which means RAS falls one NOT propagation delay after MXA goes high which is too short. To mitigate this the bootleg designers add a delay to the NOT by adding capacitance to the NOT input. The small cap then causes a delay but it is dependent on the input impedance of the gate so it's important to know roughly what that is and for LS series it is 'moderate' whereas for later series it is high and such a scheme doesn't work so well.
TBH the design is a bit c**p and should be more deterministic but hey ho!
There are similar timing concerns between the cascaded 161s and the generation of CAS which I will need to address later.
Obviously my life would have been easier if the caps were not missing!
 
Last edited:
cliff_poole

cliff_poole

Active member
vacBacker
Feedback
6 (100%)
Credits
1,069CR
r-type said:
I wish I knew what you were going on about with any of this. I'm impressed anyway. Keep it up.
Click to expand...
It really helps if you have one of these boards and have spent ages staring at it, trying to figure out what is going on. The information about what the PALs are doing might be really helpful to me as I think my problem lays there somewhere. Is it possible to de-compile a JED file to get the truth table and pinout information back ?. If so, I might be able to devise some sort of test for mine using the Retro Chip Tester.

My board is at least providing a sync signal that the test monitor can handle, and I do have a display that briefly cycles through junk on start. When I removed the bodge capacitors, the appearance of the display didn't seem to change, i.e., it stayed in sync.
 
N

NivagSwerdna

Active member
Feedback
1 (100%)
Credits
712CR
cliff_poole said:
Is it possible to de-compile a JED file to get the truth table and pinout information back ?.
Click to expand...
Absolutely. In fact I posted the equations for two of the PALs earlier in the thread. Post#9
Use the jedutil application which comes with MAME to go from JED to equations.
It's also possible to hand decode from JED if you know the internal fuse map from the PAL datasheet, there is a YouTube video of someone showing that... It's not for the faint hearted.

Video is....
"Generic Array Logic Hand Disassembly of the JEDEC File (Part 1 of 2)"
By Peepaw McDonald
It's quite a fun watch if you are that way inclined
 
Last edited:
r-type

r-type

Active member
Feedback
7 (100%)
Credits
548CR
Thanks for the replies chaps. For clarification, my level of repair expertise ends with checking voltages and re-seating chips.

The fact that you understand each other and know what you're talking about to this depth blows my mind. I wish I could do it.
 
N

NivagSwerdna

Active member
Feedback
1 (100%)
Credits
712CR
For completeness.. 5C...

Code: 
Inputs:

1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 13, 14, 15, 16, 17, 18

Outputs:

12 (Combinatorial, No output feedback, Active low)
13 (Combinatorial, Output feedback output, Active low)
14 (Combinatorial, Output feedback output, Active low)
15 (Combinatorial, Output feedback output, Active low)
16 (Combinatorial, Output feedback output, Active low)
17 (Combinatorial, Output feedback output, Active low)
18 (Combinatorial, Output feedback output, Active low)
19 (Combinatorial, No output feedback, Active low)

Equations:

/o12 = i1 & i2 & /i3 & /i4 & i5
o12.oe = vcc

/o13 = i1 & i2 & i3 & i4
o13.oe = vcc

/o14 = i1 & i2 & i3 & /i4
o14.oe = vcc

/o15 = i1 & i2 & /i3 & i4
o15.oe = vcc

/o16 = i1 & i2 & /i3 & /i4 & /i5 & /i6 & /i7 & /i8 & /i9 & /i11
o16.oe = vcc

/o17 = i1 & i2 & /i3 & /i4 & /i5 & i6
o17.oe = vcc

/o18 = i1 & i2 & /i3 & /i4 & /i5 & /i6
o18.oe = vcc

/o19 = /i1 & /i4 & i6 & i7 & i9 & /o18
o19.oe = vcc
 
N

NivagSwerdna

Active member
Feedback
1 (100%)
Credits
712CR
Thanks.

I have found a few pictures online and they all seem to have different combinations so I'm not really sure anymore!

In the Tutankham traces above it seems that RAS goes high before CAS which I think is playing fast and loose with the 4116 timing specification.

I'm trying to figure out a combination that should work.
 
N

NivagSwerdna

Active member
Feedback
1 (100%)
Credits
712CR
OK... so I thought I should just add those caps for the sake of it..

1733774383965.png

Now back to the only waveforms I really care about nRAS, nCAS and MXA

1733774492063.png

So we still aren't looking great... I'm after something like this...

2024-12-08_21-22-56.png
i.e. RAS falls in the first dip of MXA but not immediately (to let the muxes settle) and then CAS falls in the next MXA up section.

I'm not giving up!
 
N

NivagSwerdna

Active member
Feedback
1 (100%)
Credits
712CR
You probably thought I had given up.... oh no... far from it... I've been living in Konami 081 land and now I'm back!

1734896327317.png

So now I have figured out what the various signals look like it is time to see what we are actually getting...

First let's start with the E and Q which drive the 6809E (and then we can reference everything to E)... I only have a 2CH scope so this might be a bit slow...
1734896445930.png
This is looking at E & Q on the U7 marked above... (U7 refers to my earlier schematic from a 081 daughterboard implementation)... here we are around location G16.

1734896581290.png
So that looks pretty good (which is what we expected)... E falls and Q rises somewhere around the middle... 1.5MHz clock.

Next we look at the Pixel Clock relative to E...
 
N

NivagSwerdna

Active member
Feedback
1 (100%)
Credits
712CR
Now the Pixel Clock...

1734897630419.png
This is U9 pin 15... aka the first 74LS161 at H15.
We see the pixel clock is 4x 1.5MHz... i.e. 6MHz.

The E seems to fall roughly half way in the HI part of the Pixel Clock...

I'm a little surprised by the pixel clock... it is on for 1/3 and off for 2/3rds... expected that to be the other
way around... hm... I guess that is consistent with the 081 replacement if not for a real 081.
 
You must log in or register to reply here.
Top